Electroplating copper into small and some large high aspect ratio features may present various technical issues, such as seams and voids, streaks and surface roughness, and slow process throughputs. These issues may become even more severe when substrates have a thin seed, poor seed coverage, and/or when processing is performed at conditions that are close to the suppressor's cloud point, and other factors. For example, physical vapor deposition (PVD) of a seed layer often results in a film that is not conformal and has substantial variations in its thickness (e.g., having thin portions) and some gaps in coverage, especially gaps in coverage of the sidewalls and bottoms of the features. Electroplating over such seed layers may result in voids, which are unfilled pockets inside the features corresponding to the seed layer defects and caused by slower deposition rates in the areas where the seed layer is thin or missing, and other defects. Further, electro-filling large features, such as Through Silicon Vias (TSVs), may be challenging since mass transport in such features is substantially different than in smaller-size features, such as Damascene structures and vias. Most suppressors are often not sufficiently robust to address the above issues for a wide range of feature sizes. Changing suppressor formulations and concentrations can be costly and often leads to new issues associated with suppressor distribution within the solution (i.e., a cloud point) and distribution on the deposition surface. Accordingly, improved methods and apparatus to deposit copper are needed.